{"title": "Smart Vision Chip Fabricated Using Three Dimensional Integration Technology", "book": "Advances in Neural Information Processing Systems", "page_first": 720, "page_last": 726, "abstract": null, "full_text": "Smart Vision  Chip  Fabricated  Using  Three \n\nDimensional  Integration  Technology \n\nH.Kurino, M.Nakagawa, K.W.Lee, T.Nakamura, \n\nY.Yamada, K.T.Park and M.Koyanagi \n\nDept.  of Machine Intelligence \n\nand Systems Engineering, \n\nTohoku University \n\n01,  Aza-Aramaki, Aoba-ku,  Sendai \n\n980-8579, Japan \n\nkurino@sd.mech.tohoku.ac.jp \n\nAbstract \n\nThe  smart  VISIOn  chip  has  a  large  potential  for  application  in \ngeneral  purpose  high  speed  image  processing  systems.  In  order  to \nfabricate  smart  vision  chips  including  photo  detector  compactly, \nwe  have  proposed  the  application  of  three  dimensional  LSI \ntechnology  for  smart  vision  chips.  Three  dimensional  technology \nhas  great  potential  to  realize  new  neuromorphic  systems  inspired \nby not only  the biological function but also  the  biological structure. \nIn this paper, we describe our three dimensional LSI technology for \nneuromorphic circuits and the design of smart vision chips . \n\n1  Introduction \n\nRecently,  the  demand  for  very  fast  image  processing  systems  with  real  time \noperation  capability  has  significantly  increased.  Conventional  image  processing \nsystems  based  on  the  system  level  integration  of a  camera  and  a digital  processor, \ndo  not  have  the  potential  for  application  in  general  purpose  consumer  electronic \nproducts .  This  is  simply  due  to  the  cost,  size  and  complexity  of  these  systems. \nTherefore the  smart vision chip will  be an inevitable component of future  intelligent \nsystems. In  smart vision chips,  2D  images  are  simultaneously processed  in  parallel. \nTherefore  very  high  speed  image  processing  can  be  realized.  Each  pixel  includes  a \nphoto-detector.  In  order  to  receive  a  light  signal  as  much  as  possible,  the \nphoto-detector  should  occupy  a  large  proportion  of  the  pixel  area.  However  the \nsuccessive processing circuits  must become larger in each pixel to realize high level \nimage  processing.  It  is  very  difficult  to  achieve  smart  vision  chips  by  using \nconventional two  dimensional  (2D)  LSI technology because  such  smart vision chips \nhave  low  fill-factor  and  low  resolution.  This  problem  can  be  overcome  if  three \ndimensional  (3D)  integration  technology  can  be  employed  for \nthe  smart  vision \n\n\fchip.  In  this  paper,  we  propose a  smart  vision  chip  fabricated  by  three  dimensional \nintegration  technology.  We  also  discuss  the  key  technologies  for  realizing  three \ndimensional  integration  and  preliminary  test  results  of  three  dimensional  image \nsensor chips. \n\n2  Three  Dimensional  Integrated  Vision  Chips \n\nFigure  1  shows  the  cross-sectional  structure  of the  three  dimensional  integrated \nvision chip.  Several circuit layers  with different  functions  are  stacked  into one chip \nin 3D  LSI.  For example, the  first  layer consists  of a photo detector array acting like \nphoto  receptive  cells  in  the  retina,  the  second  layer  is  horizontal/bipolar  cell \ncircuits,  the  third  layer  is  ganglion  cell  circuits  and  so  on.  Each  circuit  layer  is \nstacked  and  electrically  connected  vertically  using  buried  interconnections  and \nmicro  bumps.  By  using  three  dimensional  integration  technology,  a  photo  detector \ncan be formed  with  a high fill-factor and high resolution, because  several successive \nprocessing  circuits  with  large  areas  are  formed  on  the  lower  layers  underneath  the \nphoto  detector  layer.  Every  photo  detector  is  directly  connected  with  successive \nprocessing  circuits  (ie .  horizontal  and  bipolar  cell  circuits)  in  parallel  via  the \nvertical  interconnections.  The  signals  in  every  pixel  are  simultaneously  transferred \nin  the  vertical  direction  and  processed  in  parallel  in  each  layer.  Therefore  high \nperformance  real  time  vision  chips  can  be  realized.  We  considered  the  3D  LSI \nsuitable  for  realizing  neuromorphic  LSI,  because  the  three  dimensional  structure  is \nquite  similar  to  the  structure  of the  retina  or cortex.  Three dimensional  technology \nwill  realize  new  neuromorphic  systems  inspired  by  not only  the  biological  function \nbut also the  biological structure. \n\nGlass Wafer \n\nPhotoreceptors \nLayer \n\nHorizontal  and \nBipolar  Cells \nLayer \n\nGanglion  Cells \nLayer \n\nFig.1  Cross-sectional structure of three dimensional vision chip. \n\n\fFigure  2  shows  the  neuromorphic  analog  circuits  implemented  into  3D  LSI.  The \ncircuits  are  divided  into  three  circuit  layers.  Photodiodes  and  photocircuits  are \ndesigned  on  the  first  layer.  Horizontal/bipolar cell circuits  and  ganglion  cells  are \non .. _t~~ _ ~~d  a ... n? _ }!2- !aJ~~'~ !~e~c!i~~ry.:.. ~~Sh ..... circuit \nfabricated \n: [If.t Lv..: r: \n\nlayer \n\nis \n\nI \nI \nI \nI \n\nI ~ \nI \n\nI \n\n~ -_ ...... \n\n.a  -\n\n-\n\n-\n\n-\n\n- '::_- \":::::_- ':: ':'':::::! _ _ _ __ , _____________ _ \n\nTh ird LOU \n\nI \n\n\u2022 \n\n~ .- ... -.-- ..... --- .... --- ..... --. ~ \n\n-= \n\n,-\n\nFig.2  Circuit diagram of three dimensional vision chip. \n\nPhotodiode \n\nThird  Layer \n\nFig.3  Layout of the three dimensional vision chip. \n\non  different  Si  wafers  and  stacked  into  a  3D  LSI.  Light  signals  are  converted  into \nelectrical  analog  signals  by  photodiodes  and  photocircuits  on  the  first  layer.  The \nelectric  signals  are  transferred  from  the  first  layer  to  the  second  layer  through  the \nvertical  interconnections.  The  operational  amplifiers  and  resistor  network  on  the \n\n\f", "award": [], "sourceid": 1912, "authors": [{"given_name": "Hiroyuki", "family_name": "Kurino", "institution": null}, {"given_name": "M.", "family_name": "Nakagawa", "institution": null}, {"given_name": "Kang", "family_name": "Lee", "institution": null}, {"given_name": "Tomonori", "family_name": "Nakamura", "institution": null}, {"given_name": "Yuusuke", "family_name": "Yamada", "institution": null}, {"given_name": "Ki", "family_name": "Park", "institution": null}, {"given_name": "Mitsumasa", "family_name": "Koyanagi", "institution": null}]}