Design and Implementation of a High Speed CMAC Neural Network Using Programmable CMOS Logic Cell Arrays

Part of Advances in Neural Information Processing Systems 3 (NIPS 1990)

Authors

W. Miller, Brian Box, Erich Whitney, James Glynn

Abstract

A high speed implementation of the CMAC neural network was designed using dedicated CMOS logic. This technology was then used to implement two general purpose CMAC associative memory boards for the VME bus. Each board implements up to 8 independent CMAC networks with a total of one million adjustable weights. Each CMAC network can be configured to have from 1 to 512 integer inputs and from 1 to 8 integer outputs. Response times for typical CMAC networks are well below 1 millisecond, making the networks sufficiently fast for most robot control problems, and many pattern recognition and signal processing problems.