{"title": "Analog VLSI Processor Implementing the Continuous Wavelet Transform", "book": "Advances in Neural Information Processing Systems", "page_first": 692, "page_last": 698, "abstract": null, "full_text": "Analog VLSI Processor Implementing the \n\nContinuous Wavelet Transform \n\nR. Timothy Edwards and Gert Cauwenberghs \nDepartment of Electrical and Computer Engineering \n\nJohns Hopkins University \n3400 North Charles Street \nBaltimore, MD 21218-2686 \n\n{tim,gert}@bach.ece.jhu.edu \n\nAbstract \n\nWe present an integrated analog processor for real-time wavelet decom(cid:173)\nposition and reconstruction of continuous temporal signals covering the \naudio frequency range. The processor performs complex harmonic modu(cid:173)\nlation and Gaussian lowpass filtering in 16 parallel channels, each clocked \nat a different rate, producing a multiresolution mapping on a logarithmic \nfrequency scale. Our implementation uses mixed-mode analog and dig(cid:173)\nital circuits, oversampling techniques, and switched-capacitor filters to \nachieve a wide linear dynamic range while maintaining compact circuit \nsize and low power consumption. We include experimental results on the \nprocessor and characterize its components separately from measurements \non a single-channel test chip. \n\n1 \n\nIntroduction \n\nAn effective mathematical tool for multiresolution analysis [Kais94], the wavelet transform \nhas found widespread use in various signal processing applications involving characteristic \npatterns that cover multiple scales of resolution, such as representations of speech and vision. \nWavelets offer suitable representations for temporal data that contain pertinent features both \nin the time and frequency domains; consequently, wavelet decompositions appear to be \neffective in representing wide-bandwidth signals interfacing with neural systems [Szu92]. \n\nThe present system performs a continuous wavelet transform on temporal one-dimensional \nanalog signals such as speech, and is in that regard somewhat related to silicon models \nof the cochlea implementing cochlear transforms [Lyon88], [Liu92] , [Watt92], [Lin94]. \nThe multiresolution processor we implemented expands on the architecture developed \nin [Edwa93], which differs from the other analog auditory processors in the way signal \ncomponents in each frequency band are encoded. The signal is modulated with the center \n\n\fAnalog VLSI Processor Implementing the Continuous Wavelet Transform \n\n693 \n\n1m \n\n- I \n\n_: '\\/'V \n\nset) \n\n~ Lff \nx ~ ~ yet) \n\nx(t) \n\nx(t) \n\nMultiplier \n\nh(t) \n\n(a) \n\ns'(t) \n\nLPF \n\n~ \n\nget) \n\nPrefilter \n\nMultiplexer \n\n(b) \n\nLPF \n\n~ yet) \n\nh(t) \n\nFigure 1: Demodulation systems, (a) using multiplication, and (b) multiplexing. \n\nfrequency of each channel and subsequently lowpass filtered, translating signal components \ntaken around the center frequency towards zero frequency. In particular. we consider wavelet \ndecomposition and reconstruction of analog continuous-time temporal data with a complex \nGaussian kernel according to the following formulae: \n\nYk(t) \n\n{teo x(e) exp (jWke- Q(Wk(t - e))2) de \n\n(decomposition) \n\n(1) \n\nx'(t) \n\nC 2::y\\(t) exp(-jwkt) \n\nk \n\n(reconstruction) \n\nwhere the center frequencies Wk are spaced on a logarithmic scale. The constant Q sets the \nrelative width of the frequency bins in the decomposition , and can be adjusted (together \nwith C) alter the shape of the wavelet kernel. Successive decomposition and reconstruction \ntransforms yield an approximate identity operation; it cannot be exact as no continuous \northonormal basis function exists for the CWT [Kais94]. \n\n2 Architecture \n\nThe above operations are implemented in [Edwa93] using two demodulator systems per \nchannel, one for the real component of (1), and another for the imaginary component, 90\u00b0 \nout of phase with the first. Each takes the form of a sinusoidal modulator oscillating at \nthe channel center frequency, followed by a Gaussian-shaped lowpass filter, as shown in \nFigure 1 (a). This arrangement requires a precise analog sine wave generator and an accurate \nlinear analog multiplier. In the present implementation, we circumvent both requirements \nby using an oversampled binary representation of the modulation reference signal. \n\n2.1 Multiplexing vs. MUltiplying \n\nMultiplication of an analog signal x(t) with a binary (\u00b1 1) sequence is naturally implemented \nwith high precision using a mUltiplexer, which alternates between presenting either the \ninput or its inverse -x(t) to the output. This principle is applied to simplify harmonic \nmodulation. and is illustrated in Figure 1 (b). The multiplier has been replaced by an analog \ninverter followed by a multiplexer, where the multiplexer is controlled by an oversampled \nbinary periodic sequence representing the sine wave reference. The oversampled binary \nsequence is chosen to approximate the analog sine wave as closely as possible. disregarding \ncomponents at high frequency which are removed by the subsequent lowpass filter. The \nassumption made is that no high frequency components are present in the input signal \n\n\f694 \n\nSiglUll \n\n,---- \u2022 ________ ----I In \n, \n, \ne LK/: \n: \n, \n, \n\n, \n\nI. ________________ : \n\n' \n\nR. T. EDWARDS, G. CAUWENBERGHS \n\nIn Seltrt \n\nCLK2 \n\nf ---<.-iK4 ----1:CLKS-- -: ;----- -- ---- ------1 \n\neLK] \n\nII \nII \n\nE I ' \n.---f-..., :: \n\nI \n\n\u2022 \n\" \n' I \n\n: : \n\nRet'onJlructed \n\n: cmLy, 0.,. i \n\n: \n\n\" \n.--...L..--,:: \n~~--+,~, \n\nI \n\n, \n: \n, \n: ~ ____ __________ __ J \n\nI \n\n: \n\n'-==:.J \n\nReconstruction Input \n\nMult;pl;er \n\nGaussian Filter \n\nOutput Mux ing \n\nWavelet \nReconstruction \n\nFigure 2: Block diagram of a single channel in the wavelet processor, showing test points \nA through E. \n\nunder modulation, which otherwise would convolve with corresponding high frequency \ncomponents in the binary sequence to produce low frequency distortion components at the \noutput. To that purpose, an additionallowpass filter is added in front of the multiplexer. \nResidual low-frequency distortion at the output is minimized by maximizing roll-off of the \nfilters, placing proper constraints on their cutofffrequencies, and optimally choosing the bit \nsequence in the oversampled reference [Edwa95]. Clearly, the signal accuracy that can be \nachieved improves as the length N of the sequence is extended. Constraints on the length \nN are given by the implied overhead in required signal bandwidth, power dissipation, and \ncomplexity of implementation. \n\n2.2 Wavelet Gaussian Function \n\nThe reason for choosing a Gaussian kernel in (l) is to ensure optimal support in both \ntime and frequency [Gros89]. A key requirement in implementing the Gaussian filter \nis linear phase, to avoid spectral distortion due to non-uniform group delays. A worry(cid:173)\nfree architecture would be an analog FIR filter; however the number of taps required to \naccommodate the narrow bandwidth required would be prohibitively large for our purpose. \nInstead, we approximate a Gaussian filter by cascading several first-order lowpass filters . \nFrom probabilistic arguments, the obtained lowpass filter approximates a Gaussian filter \nincreasingly well as the number of stages increases [Edwa93] . \n\n3 \n\nImplementation \n\nTwo sections of a wavelet processor, each containing 8 parallel channels, were integrated \nonto a single 4 mm x 6 mm die in 2 /lm CMOS technology. Both sections can be configured \nto perform wavelet decomposition as well as reconstruction. The block diagram for one \nof the channels is shown in Figure 2. In addition, a separate test chip was designed which \nperforms one channel of the wavelet function . Test points were made available at various \npoints for either input or output, as indicated in boldface capitals, A through E, in Figure 2. \n\nEach channel performs complex harmonic modulation and Gaussian lowpass filtering, as \ndefined above. At the front end of the chip is a sample-and-hold section to sample time(cid:173)\nmultiplexed wavelet signals for reconstruction. In cases of both signal decomposition \nand reconstruction, each channel removes the input DC component removed, filters the \nresult through the premultiplication lowpass (PML) filter, inverts the result, and passes \nboth non-inverted and inverted signals onto the multiplexer. The multiplexer output is \npassed through a postmultiplication lowpass filter (PML, same architecture) to remove high \nfrequency components of the oversampled sequence, and then passed through the Gaussian(cid:173)\nshaped lowpass filter. The cutoff frequencies of all filters are controlled by the clock rates \n\n\fAnalog VLSI Processor Implementing the Continuous Wavelet Transform \n\n695 \n\n(CLKI to CLK4 in Figure 2). The remainder of the system is for reconstruction and for \ntime-multiplexing the output. \n\n3.1 MUltiplier \n\nThe multiplier is implemented by use of the above multiplexing scheme, driven by an \noversampled binary sequence representing a sine wave. The sequence we used was 256 \nsamples in length, created from a 64-sample base sequence by reversal and inversion. The \nsequence length of256 generates a modulator wave of 4 kHz (useful for speech applications) \nfrom a clock of about 1 MHz. \n\nWe derived a sequence which, after postfiltering through a 3rd-order lowpass filter of the \nfonn of the PML prefilter (see below), produces a sine wave in which all hannonics are \nmore than 60 dB down from the primary [Edwa95]. The optimized 64-bit base sequence \nconsists of 11 zeros and 53 ones, allowing a very simple implementation in which an address \ndecoder decodes the \"zero\" bits. The binary sequence is shown in Figure 4. The magnitude \nof the prime hannonic of the sequence is approximately 1.02, within 2% of unity. \n\nThe process of reversing and inverting the sequence is simplified by using a gray code \ncounter to produce the addresses for the sequence, with only a small amount of combinatorial \nlogic needed to achieve the desired result [Edwa95]. It is also straightforward to generate \nthe addresses for the cosine channel, which is 90\u00b0 out of phase with the original. \n\n3.2 Linear Filtering \n\nAll filters used are implemented as linear cascades of first-order, single-pole filter sections. \nThe number of first-order sections for the PML filters is 3. The number of sections for the \n\"Gaussian\" filter is 8, producing a suitable approximation to a Gaussian filter response for \nall frequencies of interest (Figure 5). \n\nFigure 3 shows one first-order lowpass section of the filters as implemented. This standard \n\nv,,, \n\n+ \n\n>-.+--o va\"' \n\nFigure 3: Single discrete-time lowpass filter section. \n\nswitched-capacitor circuit implements a transfer function containing a single pole, approx(cid:173)\nimately located in the Laplace domain at s = Is / a for large values of the parameter a, with \nIs being the sampling frequency. The value for this parameter a is fixed at the design stage \nas the ratio of two capacitors in Figure 3, and was set to be 15 for the The PML filters and \n12 for the Gaussian filters. \n\n4 Measured Results \n\n4.1 Sine wave modulator \n\nWe tested the accuracy of the sine wave modulation signal by applying two constant voltages \nat test points A and B, such that the sine wave modulation signal is effectively multiplied \n\n\f696 \n\nR. T. EDWARDS, G. CAUWENBERGHS \n\nSine sequence and filtered sine wave output \n\n-1.5 L -__ _ - - ' __ __ - ' -_ __ _ ........ _ __ _ - ' -_ __ _ .J...J \n250 \n\n200 \n\n100 \n\no \n\nBinary sine sequence \nSimulated filtered output \nMeasured output \n\n150 \n\nx \n\n50 \n\nTime (us) \n\nFigure 4: Filtered sine wave output. \n\nby a constant. The output of the mUltiplier is filtered and the output taken at test point D, \nbefore the Gaussian filter. Figure 4 shows the (idealized) multiplexer output at test point \nC, which accurately creates the desired binary sequence. Figure 4 also shows the measured \nsine wave after filtering with the PML filter and the expected output from the simulation \nmodel, using a deviating value of 8.0 for the capacitor ratio a, as justified below. FFT \nanalysis of Figure 4 has shown that the resulting sine wave has all harmonics below about \n-49 dB . This is in good agreement with the simulation model, provided a correction is made \nfor the value of the capacitor ratio a to account for fringe and (large) parasitic capacitances. \nThe best fit for the measured data from the postmultiplication filter is a = 8.0, compared to \nthe desired value of a = 15.0. The transform of the simulated output shown in the figure \ntakes into account the smaller value of a. Because the postmultiplication filter is followed \nby the Gaussian filter, the bandwidth of the output can be directly controlled by proper \nclocking ofthe Gaussian filter, so the distortion in the sine wave is ultimately much smaller \nthan that measured at the output of the postmultiplication filter. \n\n4.2 Gaussian filter \n\nThe Gaussian filter was tested by applying a signal at test point D and measuring the \nresponse at test point E. Figure 5 shows the response of the Gaussian filter as compared to \nexpected responses. There are two sets of curves, one for a filter clocked at 64 kHz, and the \nother clocked at 128 kHz; these curves are normalized by plotting time relative to the clock \nfrequency is . The solid line indicates the best match for an 8th-order lowpass filter, using \nthe capacitor ratio, a, as a fitting parameter. The best-fit value of a is approximately 6.8. \nThis is again much lower than the capacitor area ratio of 12 on the chip. The dotted line is \nthe response of the ideal Gaussian characteristic exp ( _w 2 / (2aw~)) approximated by the \ncascade of first-order sections with capacitor ratio a. \n\nFigure 5 (b) shows the measured phase response of the Gaussian filter for the 128 kHz \nclock. The phase response is approximately linear throughout the passband region. \n\n\fAnalog VLSI Processor Implementing the Continuous Wavelet Transform \n\n697 \n\no~~~~--~-=~~~~~~~--~ \n\niii'-10 \n~ \n