Digital Boltzmann VLSI for constraint satisfaction and learning

Part of Advances in Neural Information Processing Systems 6 (NIPS 1993)

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Michael Murray, Ming-Tak Leung, Kan Boonyanit, Kong Kritayakirana, James Burg, Gregory Wolff, Tokahiro Watanabe, Edward Schwartz, David Stork, Allen M. Peterson


We built a high-speed, digital mean-field Boltzmann chip and SBus board for general problems in constraint satjsfaction and learning. Each chip has 32 neural processors and 4 weight update processors, supporting an arbitrary topology of up to 160 functional neurons. On-chip learning is at a theoretical maximum rate of 3.5 x 108 con(cid:173) nection updates/sec; recall is 12000 patterns/sec for typical condi(cid:173) tions. The chip's high speed is due to parallel computation of inner products, limited (but adequate) precision for weights and activa(cid:173) tions (5 bits), fast clock (125 MHz), and several design insights.